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1. general description the pca9545a is a quad bi-directional translating switch controlled via the i 2 c-bus. the scl/sda upstream pair fans out to four downstream pairs, or channels. any individual scx/sdx channel or combination of channels can be selected, determined by the contents of the programmable control register. four interrupt inputs, int0 to int3, one for each of the downstream pairs, are provided. one interrupt output, int, acts as an and of the four interrupt inputs. an active low reset input allows the pca9545a to recover from a situation where one of the downstream i 2 c-buses is stuck in a low state. pulling the reset pin low resets the i 2 c-bus state machine and causes all the channels to be deselected as does the internal power-on reset function. the pass gates of the switches are constructed such that the v dd pin can be used to limit the maximum high voltage which will be passed by the pca9545a. this allows the use of different bus voltages on each pair, so that 1.8 v or 2.5 v or 3.3 v parts can communicate with 5 v parts without any additional protection. external pull-up resistors pull the bus up to the desired voltage level for each channel. all i/o pins are 5 v tolerant. 2. features n 1-of-4 bi-directional translating switches n i 2 c-bus interface logic; compatible with smbus standards n 4 active low interrupt inputs n active low interrupt output n active low reset input n 2 address pins allowing up to 4 devices on the i 2 c-bus n channel selection via i 2 c-bus, in any combination n power-up with all switch channels deselected n low r on switches n allows voltage level translation between 1.8 v, 2.5 v, 3.3 v and 5 v buses n no glitch on power-up n supports hot insertion n low stand-by current n operating power supply voltage range of 2.3 v to 5.5 v n 5 v tolerant inputs n 0 khz to 400 khz clock frequency n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 n latch-up protection exceeds 100 ma per jesd78 pca9545a 4-channel i 2 c switch with interrupt logic and reset rev. 03 3 march 2005 product data sheet
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 2 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset n three packages offered: so20, tssop20, and hvqfn20 3. ordering information standard packing quantities and other packaging data are available at www .standardproducts .philips .com/pac kaging . 4. marking table 1: ordering information t amb = C40 cto+85 c type number package name description version PCA9545ABS hvqfn20 plastic thermal enhanced very thin quad ?at package; no leads; 20 terminals; body 5 5 0.85 mm sot662-1 pca9545ad so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1 pca9545apw tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 table 2: marking codes type number topside mark PCA9545ABS 9545a pca9545ad pca9545ad pca9545apw pa9545a
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 3 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 5. block diagram fig 1. block diagram of pca9545a switch control logic pca9545a power-on reset 002aab168 sc0 sc1 sc2 sc3 sd0 sd1 sd2 sd3 v ss v dd reset i 2 c-bus control input filter scl sda a0 a1 interrupt logic int0 to int3 int
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 4 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin con?guration for so20 fig 3. pin con?guration for tssop20 fig 4. pin con?guration for hvqfn20 (transparent top view) pca9545ad a0 v dd a1 sda reset scl int0 int sd0 sc3 sc0 sd3 int1 int3 sd1 sc2 sc1 sd2 v ss int2 002aab165 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 v dd sda scl int sc3 sd3 int3 sc2 sd2 int2 a0 a1 reset int0 sd0 sc0 int1 sd1 sc1 v ss pca9545apw 002aab166 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 v dd sda scl int sc3 sd3 int3 sc2 a0 a1 reset int0 sd0 sc0 int1 sd1 sc1 v ss 002aab167 PCA9545ABS transparent top view 5 11 4 12 3 13 2 14 1 15 6 7 8 9 10 20 19 18 17 16 terminal 1 index area sd2 int2 table 3: pin description symbol pin description so, tssop hvqfn a0 1 19 address input 0 a1 2 20 address input 1 reset 3 1 active low reset input int0 4 2 active low interrupt input 0 sd0 5 3 serial data 0 sc0 6 4 serial clock 0 int1 7 5 active low interrupt input 1 sd1 8 6 serial data 1
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 5 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset [1] hvqfn package die supply ground is connected to both the v ss pin and the exposed center pad. the v ss pin must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the pcb in the thermal pad region. 7. functional description refer to figure 1 bloc k diag r am of pca9545a on page 3 . 7.1 device address following a start condition, the bus master must output the address of the slave it is accessing. the address of the pca9545a is shown in figure 5 . to conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled high or low. the last bit of the slave address de?nes the operation to be performed. when set to logic 1, a read is selected while a logic 0 selects a write operation. sc1 9 7 serial clock 1 v ss 10 8 [1] supply ground int2 11 9 active low interrupt input 2 sd2 12 10 serial data 2 sc2 13 11 serial clock 2 int3 14 12 active low interrupt input 3 sd3 15 13 serial data 3 sc3 16 14 serial clock 3 int 17 15 active low interrupt output scl 18 16 serial clock line sda 19 17 serial data line v dd 20 18 supply voltage table 3: pin description continued symbol pin description so, tssop hvqfn fig 5. slave address 002aab169 1 1 1 0 0 a1 a0 r/w fixed hardware selectable
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 6 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 7.2 control register following the successful acknowledgement of the slave address, the bus master will send a byte to the pca9545a, which will be stored in the control register. if multiple bytes are received by the pca9545a, it will save the last byte received. this register can be written and read via the i 2 c-bus. 7.2.1 control register de?nition one or several scx/sdx downstream pair, or channel, is selected by the contents of the control register. this register is written after the pca9545a has been addressed. the 4 lsbs of the control byte are used to determine which channel is to be selected. when a channel is selected, the channel will become active after a stop condition has been placed on the i 2 c-bus. this ensures that all scx/sdx lines will be in a high state when the channel is made active, so that no false conditions are generated at the time of connection. remark: several channels can be enabled at the same time. example: b3 = 0, b2 = 1, b1 = 1, b0 = 0, means that channel 0 and channel 3 are disabled and channel 1 and channel 2 are enabled. care should be taken not to exceed the maximum bus capacity. fig 6. control register 002aab170 int 3 int 2 int 1 int 0 b3 b2 b1 b0 channel selection bits (read/write) 76543210 interrupt bits (read only) channel 0 channel 1 channel 2 channel 3 int0 int1 int2 int3 table 4: control register: writechannel selection; readchannel status int3 int2 int1 int0 b3 b2 b1 b0 command xxxxxxx 0 channel 0 disabled 1 channel 0 enabled xxxxxx 0 x channel 1 disabled 1 channel 1 enabled xxxxx 0 xx channel 2 disabled 1 channel 2 enabled xxxx 0 xxx channel 3 disabled 1 channel 3 enabled 00000000no channel selected; power-up/reset default state
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 7 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 7.2.2 interrupt handling the pca9545a provides 4 interrupt inputs, one for each channel, and one open-drain interrupt output. when an interrupt is generated by any device, it will be detected by the pca9545a and the interrupt output will be driven low. the channel does not need to be active for detection of the interrupt. a bit is also set in the control register. bit 4 through bit 7 of the control register corresponds to channel 0 through channel 3 of the pca9545a, respectively. therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the control register when a read is accomplished. likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. the master can then address the pca9545a and read the contents of the control register to determine which channel contains the device generating the interrupt. the master can then recon?gure the pca9545a to select this channel, and locate the device generating the interrupt and clear it. it should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. the interrupt inputs may be used as general purpose inputs if the interrupt function is not required. if unused, interrupt input(s) must be connected to v dd through a pull-up resistor. remark: several interrupts can be active at the same time. example: int3 = 0, int2 = 1, int1 = 1, int0 = 0, means that there is no interrupt on channel 0 and channel 3, and there is interrupt on channel 1 and channel 2. 7.3 reset input the reset input is an active low signal which may be used to recover from a bus fault condition. by asserting this signal low for a minimum of t wl , the pca9545a will reset its registers and i 2 c-bus state machine and will deselect all channels. the reset input must be connected to v dd through a pull-up resistor. table 5: control register: readinterrupt int3 int2 int1 int0 b3 b2 b1 b0 command xxx 0 xxxx no interrupt on channel 0 1 interrupt on channel 0 xx 0 xxxxx no interrupt on channel 1 1 interrupt on channel 1 x 0 xxxxxx no interrupt on channel 2 1 interrupt on channel 2 0 xxxxxxx no interrupt on channel 3 1 interrupt on channel 3
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 8 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 7.4 power-on reset when power is applied to v dd , an internal power-on reset (por) holds the pca9545a in a reset condition until v dd has reached v por . at this point, the reset condition is released and the pca9545a registers and i 2 c-bus state machine are initialized to their default statesall zeroescausing all the channels to be deselected. thereafter, v dd must be lowered below 0.2 v to reset the device. 7.5 voltage translation the pass gate transistors of the pca9545a are constructed such that the v dd voltage can be used to limit the maximum voltage that will be passed from one i 2 c-bus to another. figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data speci?ed in section 11 static char acter istics of this data sheet). in order for the pca9545a to act as a voltage translator, the v o(sw) voltage should be equal to, or lower than the lowest bus voltage. for example, if the main bus was running at 5 v, and the downstream buses were 3.3 v and 2.7 v, then v o(sw) should be equal to or below 2.7 v to effectively clamp the downstream bus voltages. looking at figure 7 , we see that v o(sw)(max) will be at 2.7 v when the pca9545a supply voltage is 3.5 v or lower, so the pca9545a supply voltage could be set to 3.3 v. pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see figure 14 ). more information can be found in application note an262: pca954x family of i2c/smbus multiplexers and switches . (1) maximum (2) typical (3) minimum fig 7. pass gate voltage versus supply voltage v dd (v) 2.0 5.5 4.5 3.0 4.0 002aaa964 3.0 2.0 4.0 5.0 v o(sw) (v) 1.0 3.5 5.0 2.5 (1) (2) (3)
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 9 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 8. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 8.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 8 ). 8.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is de?ned as the start condition (s). a low-to-high transition of the data line while the clock is high is de?ned as the stop condition (p) (see figure 9 ). fig 8. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 9. de?nition of start and stop conditions mba608 sda scl p stop condition sda scl s start condition
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 10 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 8.3 system con?guration a device generating a message is a transmitter, a device receiving is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 10 ). 8.4 acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse; setup and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. fig 10. system con?guration 002aaa966 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl i 2 c multiplexer slave fig 11. acknowledgement on the i 2 c-bus 002aaa987 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 11 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 8.5 bus transactions data is transmitted to the pca9545a control register using the write mode as shown in figure 12 . data is read from pca9545a using the read mode as shown in figure 13 . fig 12. write control register fig 13. read control register 002aab172 xxxxb3b2b1b0 1 1 0 0 a1 a0 0 a s 1 a p slave address start condition r/w acknowledge from slave acknowledge from slave control register sda stop condition 002aab173 int3 int2 int1 int0 b3 b2 b1 b0 1 1 0 0 a1 a0 1 a s 1 na p slave address start condition r/w acknowledge from slave no acknowledge from master control register sda stop condition last byte
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 12 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 9. application design-in information (1) if the device generating the interrupt has an open-drain output structure or can be 3-stated, a pull-up resistor is required. if the device generating the interrupt has a totem-pole output structure and cannot be 3-stated, a pull-up resistor is not required. the interrupt inputs should not be left ?oating. fig 14. typical application pca9545a sd0 sc0 a1 a0 v ss sda scl reset v dd = 3.3 v v dd = 2.7 v to 5.5 v i 2 c/smbus master 002aab171 sda scl channel 0 v = 2.7 v to 5.5 v int int0 see note (1) sd1 sc1 channel 1 v = 2.7 v to 5.5 v int1 see note (1) sd2 sc2 channel 2 v = 2.7 v to 5.5 v int2 see note (1) sd3 sc3 channel 3 v = 2.7 v to 5.5 v int3 see note (1)
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 13 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 10. limiting values [1] the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create j unction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. table 6: limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to v ss (ground = 0 v). [1] symbol parameter conditions min max unit v dd supply voltage C0.5 +7.0 v v i input voltage C0.5 +7.0 v i i input current - 20 ma i o output current - 25 ma i dd supply current - 100 ma i ss ground supply current - 100 ma p tot total power dissipation - 400 mw t stg storage temperature C60 +150 c t amb operating ambient temperature C40 +85 c
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 14 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 11. static characteristics [1] for operation between published voltage ranges, refer to the worst-case parameter in both ranges. [2] v dd must be lowered to 0.2 v in order to reset part. table 7: static characteristics v dd = 2.3 v to 3.6 v; v ss = 0 v; t amb = C 40 c to +85 c; unless otherwise speci?ed. see t ab le 8 on page 15 for v dd = 4.5 v to 5.5 v. [1] symbol parameter conditions min typ max unit supply v dd supply voltage 2.3 - 3.6 v i dd supply current operating mode; v dd = 3.6 v; no load; v i =v dd or v ss ; f scl = 100 khz -1030 m a i stb standby current standby mode; v dd = 3.6 v; no load; v i =v dd or v ss - 0.1 1 m a v por power-on reset voltage no load; v i =v dd or v ss [2] - 1.6 2.1 v input scl; input/output sda v il low-level input voltage C0.5 - 0.3v dd v v ih high-level input voltage 0.7v dd -6 v i ol low-level output current v ol = 0.4 v 3 7 - ma v ol = 0.6 v 6 10 - ma i l leakage current v i =v dd or v ss C1 - +1 m a c i input capacitance v i =v ss -1013pf select inputs a0, a1, int0 to int3, reset v il low-level input voltage C0.5 - 0.3v dd v v ih high-level input voltage 0.7v dd -v dd + 0.5 v i li input leakage current pin at v dd or v ss C1 - +1 m a c i input capacitance v i =v ss - 1.6 3 pf pass gate r on on-state resistance v dd = 3.67 v; v o = 0.4 v; i o =15ma 5 11 30 w v dd = 2.3 v to 2.7 v; v o = 0.4 v; i o =10ma 71655 w v o(sw) switch output voltage v i(sw) =v dd = 3.3 v; i o(sw) = C100 m a - 1.9 - v v i(sw) =v dd = 3.0 v to 3.6 v; i o(sw) = C100 m a 1.6 - 2.8 v v i(sw) =v dd = 2.5 v; i o(sw) = C100 m a - 1.5 - v v i(sw) =v dd = 2.3 v to 2.7 v; i o(sw) = C100 m a 1.1 - 2.0 v i l leakage current v i =v dd or v ss C1 - +1 m a c io input/output capacitance v i =v ss -35 pf int output i ol low-level output current v ol = 0.4 v 3 - - ma i oh high-level output current - - +10 m a
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 15 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset [1] for operation between published voltage ranges, refer to the worst-case parameter in both ranges. [2] v dd must be lowered to 0.2 v in order to reset part. table 8: static characteristics v dd = 4.5 v to 5.5 v; v ss = 0 v; t amb = C 40 c to +85 c; unless otherwise speci?ed. see t ab le 7 on page 14 for v dd = 2.3 v to 3.6 v. [1] symbol parameter conditions min typ max unit supply v dd supply voltage 4.5 - 5.5 v i dd supply current operating mode; v dd = 5.5 v; no load; v i =v dd or v ss ; f scl = 100 khz - 25 100 m a i stb standby current standby mode; v dd = 5.5 v; no load; v i =v dd or v ss - 0.3 1 m a v por power-on reset voltage no load; v i =v dd or v ss [2] - 1.7 2.1 v input scl; input/output sda v il low-level input voltage C0.5 - 0.3v dd v v ih high-level input voltage 0.7v dd -6 v i ol low-level output current v ol = 0.4 v 3 - - ma v ol = 0.6 v 6 - - ma i l leakage current v i =v ss C1 - 1 m a c i input capacitance v i =v ss -1013pf select inputs a0, a1, int0 to int3, reset v il low-level input voltage C0.5 - 0.3v dd v v ih high-level input voltage 0.7v dd -v dd + 0.5 v i li input leakage current v i =v dd or v ss C1 - +1 m a c i input capacitance v i =v ss -25 pf pass gate r on on-state resistance v dd = 4.5 v to 5.5 v; v o = 0.4 v; i o =15ma 4924 w v o(sw) switch output voltage v i(sw) =v dd = 5.0 v; i o(sw) = C100 m a - 3.6 - v v i(sw) =v dd = 4.5 v to 5.5 v; i o(sw) = C100 m a 2.6 - 4.5 v i l leakage current v i =v dd or v ss C1 - +1 m a c io input/output capacitance v i =v ss -35 pf int output i ol low-level output current v ol = 0.4 v 3 - - ma i oh high-level output current - - +10 m a
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 16 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 12. dynamic characteristics [1] pass gate propagation delay is calculated from the 20 w typical r on and the 15 pf load capacitance. [2] a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ih(min) of the scl signal) in order to bridge the unde?ned region of the falling edge of scl. [3] c b = total capacitance of one bus line in pf. [4] measurements taken with 1 k w pull-up resistor and 50 pf load. table 9: dynamic characteristics symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max t pd propagation delay from sda to sdn, or scl to scn - 0.3 [1] - 0.3 [1] ns f scl scl clock frequency 0 100 0 400 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - m s t hd;sta hold time (repeated) start condition. after this period, the ?rst clock pulse is generated. 4.0 - 0.6 - m s t low low period of the scl clock 4.7 - 1.3 - m s t high high period of the scl clock 4.0 - 0.6 - m s t su;sta setup time for a repeated start condition 4.7 - 0.6 - m s t su;sto setup time for stop condition 4.0 - 0.6 - m s t hd;dat data hold time 0 [2] 3.45 0 [2] 0.9 m s t su;dat data setup time 250 - 100 - ns t r rise time of both sda and scl signals - 1000 20 + 0.1c b [3] 300 ns t f fall time of both sda and scl signals - 300 20 + 0.1c b [3] 300 m s c b capacitive load for each bus line - 400 - 400 m s t sp pulse width of spikes which must be suppressed by the input ?lter - 50 - 50 ns t vd;dat data valid time high-to-low [4] -1 - 1 m s low-to-high [4] - 0.6 - 0.6 m s t vd;ack data valid acknowledge - 1 - 1 m s int t v(intnn-intn) valid time from intn to int signal - 4 - 4 m s t d(intnn-intn) delay time from intn to int inactive - 2 100 2 m s t w(rej)l low-level rejection time intn inputs 1 - 1 - m s t w(rej)h high-level rejection time intn inputs 0.5 - 0.5 - m s reset t w(rst)l low-level reset time 4 - 4 - ns t rst reset time (sda clear) 500 - 500 - ns t rec;sta recovery time to start condition 0 - 0 - ns
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 17 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset fig 15. de?nition of timing on the i 2 c-bus t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl 002aaa986 fig 16. de?nition of reset timing sda scl 002aab174 t rst 50 % 30 % 50 % 50 % 50 % t rec;sta t w(rst)l reset ledx led off start t rst ack or read cycle rise and fall times, refer to v il and v ih . fig 17. i 2 c-bus timing diagram scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 002aab175 t su;sto protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) 1 /f scl t r t vd;dat
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 18 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 13. test information fig 18. expanded view of read input port register scl 002aab176 21 0 ap 70 % 30 % sda input 50 % int t v(intnn - intn) t d(intnn - intn) de?nitions test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. fig 19. test circuitry for switching times pulse generator v o c l 50 pf r l 500 w 002aab177 r t v i v dd v dd d.u.t.
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 19 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 14. package outline fig 20. package outline sot163-1 (so20) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x q a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 99-12-27 03-02-19
philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 20 of 27 fig 21. package outline sot360-1 (tssop20) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 110 20 11 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1
philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 21 of 27 fig 22. package outline sot662-1 (hvqfn20) 0.65 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 5.1 4.9 d h 3.25 2.95 y 1 5.1 4.9 3.25 2.95 e 1 2.6 e 2 2.6 0.38 0.23 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot662-1 mo-220 - - - - - - 0.75 0.50 l 0.1 v 0.05 w 0 2.5 5 mm scale sot662-1 hvqfn20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 610 20 16 15 11 5 1 x d e c b a e 2 terminal 1 index area terminal 1 index area 01-08-08 02-10-22 a c c b v m w m e (1) d (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included.
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 22 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 15. soldering 15.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 15.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 cto270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 15.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 23 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 15.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 15.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. table 10: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 24 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vsop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 16. abbreviations table 11: abbreviations acronym description cdm charged device model esd electro static discharge hbm human body model ic integrated circuit lsb least signi?cant bit mm machine model msb most signi?cant bit pcb printed-circuit board por power-on reset
9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 25 of 27 philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 17. revision history table 12: revision history document id release date data sheet status change notice doc. number supersedes pca9545a_3 20050303 product data sheet - 9397 750 14311 pca9545a_2 modi?cations: ? the format of this data sheet has been redesigned to comply with the new presentation and information standard of philips semiconductors. ? section 2 f eatures on page 1 : 9th bullet: changed rds on to r on ? figure 4 pin con? gur ation f or hvqfn20 (tr ansparent top vie w) on page 4 : added pin 1 indicator notch and center pad. ? t ab le 3 pin descr iption on page 4 : added t ab le note 1 and its reference at hvqfn pin 8. ? section 7.5 v oltage tr anslation on page 8 : C figure 7 : title changed from v pass voltage versus v dd to pass gate voltage versus supply voltage; within graphic changed v pass (v) to v o(sw) (v) C 2nd paragraph: changed v pass to v o(sw) ; changed v pass(max) to v o(sw)(max) ? t ab le 6 limiting v alues on page 13 : remove (old) table note [1], as it is now covered by section 19 de? nitions on page 26 . ? t ab le 7 static char acter istics on page 14 : C changed symbol r on to r on ; changed parameter from switch resistance to on-state resistance C changed symbol v pass to v o(sw) C under conditions column for v o(sw) : changed v swin to v i(sw) ; changed i swout to i o(sw) C added (new) t ab le note 1 . ? t ab le 8 static char acter istics on page 15 : C changed symbol r on to r on ; changed parameter from switch resistance to on-state resistance C changed symbol v pass to v o(sw) C under conditions column for v o(sw) : changed v swin to v i(sw) ; changed i swout to i o(sw) ? t ab le 9 dynamic char acter istics on page 16 : C changed symbol t r to t r ; changed symbol t f to t f (also in figure 15 on page 17 ) C changed symbols t vd;datl and t vd;dath to t vd;dat and added conditions indicating high-to-low and low-to-high transitions C changed symbol t iv to t v(intnn-intn) (also in figure 18 on page 18 ) C changed symbol t ir to t d(intn-intn) (also in figure 18 on page 18 ) C changed symbol l pwr to t w(rej)l C changed symbol h pwr to t w(rej)h C changed symbol t wl(rst) to t w(rst)l (also in figure 16 on page 17 ) ? added section 16 ab bre viations . pca9545a_2 20040929 objective data sheet - 9397 750 13989 pca9545a_1 pca9545a_1 20040728 objective data sheet - 9397 750 13309 -
philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 9397 750 14311 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 3 march 2005 26 of 27 18. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 19. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 20. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 21. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2005 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 3 march 2005 document number: 9397 750 14311 published in the netherlands philips semiconductors pca9545a 4-channel i 2 c switch with interrupt logic and reset 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 control register . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2.1 control register de?nition . . . . . . . . . . . . . . . . . 6 7.2.2 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . 7 7.3 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.4 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 8 7.5 voltage translation . . . . . . . . . . . . . . . . . . . . . . 8 8 characteristics of the i 2 c-bus. . . . . . . . . . . . . . 9 8.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.2 start and stop conditions . . . . . . . . . . . . . . 9 8.3 system con?guration . . . . . . . . . . . . . . . . . . . 10 8.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.5 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 11 9 application design-in information . . . . . . . . . 12 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 11 static characteristics. . . . . . . . . . . . . . . . . . . . 14 12 dynamic characteristics . . . . . . . . . . . . . . . . . 16 13 test information . . . . . . . . . . . . . . . . . . . . . . . . 18 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 15 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 15.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 15.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 15.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22 15.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 23 15.5 package related soldering information . . . . . . 23 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 18 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 26 19 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 20 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 21 contact information . . . . . . . . . . . . . . . . . . . . 26

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